Abstract: The partial connection and the implementation diversity of routers are exploited. Network on chip has emerged as a promising solution to future System on Chip (SOC). Network on Chip (NOC) topology synthesis determine the connection of the routers. In the existing topology synthesis method consider only a single implementation for each size of the router. To tackle this drawback, we propose a Novel NOC topology synthesis method where the implementation diversity of the routers is exploited to produce optimal topologies in terms of area and or the power consumption. Here the algorithm used produces a single optimised route which reduces the route discovery time, number of hops, and the energy consumption.

Keywords: network on chip (NOC), system on chip (SOC), synthesis, routers.